1. Technical Field
The present invention relates to memory design and, in particular, to built-in self repair. Still more particularly, the present invention provides a method and apparatus for providing built-in self repair with row shifting.
2. Description of the Related Art
A memory circuit is like an electronic checkerboard, with each square holding one bit of data or instruction. Each square, also referred to as a “cell,” has a separate address and can be manipulated independently. Cells are addressed as rows of cells. When manufacturing a memory circuit, or chip, rows must be addressed with row select signals and word line signals. FIG. 1 is a diagram illustrating an example of a basic memory structure. The memory structure includes memory bit cells 102, 104. Control/predecoder 116 receives control inputs and asserts word lines through word line decoders and drivers 120, 130, 140, and 150. Inputs and Outputs are provided through sense amplifiers, multiplexors, and input/output drivers 112, 114.
FIG. 2 illustrates the details of a word line decoder and driver area for the access of word lines for standard memory. Control inputs for rows 0-7 are provided to row decoders 210. The row decoders generate row select signals rsel0 to rsel7. Word line drivers 220 receive the row select signals and generate word line signals wl0 to wl7. The example depicted in FIG. 2 shows eight rows; however, more or fewer rows may be included. More particularly, the memory structure will likely include thousands of rows of memory cells.
Due to difficulties in manufacturing a memory with a high number of elements, bad rows or groups of rows are likely to occur. After fabrication, a memory chip may be tested to determine whether bad cells exists. However, discarding a memory chip for one bad memory cell or row of cells is costly. Therefore, memory circuits are designed with built-in self repair (BISR) to improve manufacturing yield. There are many types of BISR schemes available, such as row redundancy, column redundancy, block redundancy, and I/O redundancy.
Almost all current row redundancy BISR schemes use address remapping, which compares the incoming memory row address to stored defective row addresses to tell if the incoming memory row address is a defective row address. If the incoming row address is a defective row address, then the access to the defective row is disabled and it is remapped to an address of a redundant row. A defective row can be disabled during every access cycle (on the fly) or only during the start of all memory access.
These schemes require extra address access time, because of the row address remap. Also, to disable the defective row on the fly requires that the address is set well in advance to do the comparison and disable the defective row. This adds large extra penalty into the address setup time and is generally not acceptable in most designs. Furthermore, address remap circuitry adds to the complexity and layout area of the memory architecture.
Therefore, it would be advantageous to provide an improved method and apparatus for built-in self repair of rows in a memory circuit.